1. Field of the Invention
The present invention relates to a semiconductor device, and, specifically to a structure for reducing current consumption in a semiconductor device including a logic gate consisting of CMOS transistors (complementary insulated gate type field effect transistors) without affecting operating characteristics thereof. More specifically, the present invention relates to a structure for reducing subthreshold current of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
A CMOS circuit has been well known as a semiconductor circuit of which power consumption is extremely small.
FIG. 60 shows a structure of a general CMOS inverter.
Referring to FIG. 60, the CMOS inverter includes a p channel MOS transistor (insulated gate type field effect transistor) PT provided between a power supply node 1900 receiving one operating power supply voltage Vcc and an output node 1901 and receiving at its gate an input signal IN; and an n channel MOS transistor NT provided between the other power supply node 1902 receiving the other operating power supply voltage Vss (generally, ground potential) and output node 1901 and receiving at its gate the input signal IN. There is a load capacitance C at output node 1901. When input signal IN is at a low level, p channel MOS transistor PT turns on, n channel MOS transistor NT turns off, load capacitance C is charged through p channel MOS transistor PT, and an output signal OUT attains to the power supply voltage level Vcc. When charging of the load capacitance C is completed, source and drain of p channel MOS transistor PT come to have the same potential, and thus the transistor PT turns off. Therefore, at this time, current does not flow, and power consumption is negligible.
When input signal IN is at a high level, p channel MOS transistor PT turns off, n channel MOS transistor NT turns on, and load capacitance C is discharged to the level of the other power supply potential Vss through n channel MOS transistor NT. When the discharge is completed, the source and drain of n channel MOS transistor NT come to have the same potential, and thus the transistor NT turns off. Therefore, in this state also, power consumption is negligible.
A drain current IL flowing through a MOS transistor can be represented by a function of a gate-source voltage of the MOS transistor. When the absolute value of the gate-source voltage becomes larger than the absolute value of the threshold voltage of an MOS transistor, a large drain current flows. Even when the absolute value of the gate-source voltage becomes not higher than that of absolute value of the threshold voltage, the drain current is not completely reduced to 0. This drain current flowing under such a voltage is referred to as subthreshold current which is exponentially proportional to the gate-source voltage.
FIG. 61 shows subthreshold current characteristic of an n channel MOS transistor. Referring to FIG. 61, the abscissa represents gate-source voltage VGS, and the ordinate represents logarithmic value of drain current IL. In FIG. 61, linear regions of lines I and II each represent the subthreshold current. The threshold voltage is defined as the gate-source voltage providing a prescribed current in this subthreshold current region. For example, in MOS transistor having the gate width (channel width) of 10 .mu.m, the gate-source voltage causing a drain current flow of 10 mA is defined as the threshold voltage. FIG. 61 represents the prescribed current I0 and the threshold voltages VT0 and VT1.
As the MOS transistor has been made smaller and smaller, the power supply voltage Vcc decreases in accordance with the scaling rule. Therefore, the absolute value Vth of the threshold voltage of the MOS transistor must be decreased similarly in accordance with the scaling rule in order to improve performance of the MOS transistor. In the CMOS inverter shown in FIG. 60, for example, assume that the power supply voltage Vcc is 5 V and the threshold voltage Vth of n channel MOS transistor NT is 1 V. When input signal IN changes from 0 V to a value larger than 1 V, a large drain current flow is generated, starting discharging of load capacitance C. On the other hand, when the power supply voltage Vcc is lowered to 3 V, for example, while maintaining the threshold voltage Vth at the same value, the load capacitance C can be discharged with large current only when the input signal IN exceeds 1 V to turn on the n channel MOS transistor NT. More specifically, when the power supply voltage Vcc is 5 V, discharge of capacitive load starts at 1/5 of the amplitude of the input signal IN. Meanwhile, when the power supply voltage Vcc is 3 V, discharge of capacitive load C starts at 1/3 of the amplitude of input signal IN. Namely, input/output response characteristic is degraded, and hence high speed operation cannot be ensured. Therefore, the absolute value Vth of the threshold voltage needs to be scaled similarly down as the power supply voltage. However, as shown in FIG. 61, when the threshold voltage VT1 is lowered to the threshold voltage VT0, the subthreshold current characteristic changes from that represented by the line I to that of the line II. Accordingly, the subthreshold current when the gate voltage is 0 V (Vss level) rises from IL1 to IL0, increasing current consumption. Thus, difficulty is encountered in scaling down the absolute value Vth of the threshold voltage in the similar manner as the power supply voltage and in realizing superior operating characteristics, especially high speed operation.
Structures for suppressing subthreshold current without degrading high speed operation characteristic have been disclosed in pages 47 and 48, and in pages 83 and 84 of 1993 Symposium on VLSI Circuit, Digest of Technical Pacers, by Horiguchi et al. and Takashima et al., respectively.
FIG. 62 shows a structure of a power supply line disclosed by Horiguchi et al. in the above described article. FIG. 62 shows, as an example of a CMOS circuit, n cascade connected CMOS inverters f1 to fn. Each of inverters f1 to f4 has the same structure as that shown in FIG. 60.
In a path for supplying one operating power supply voltage, a first power supply line 1911 is connected to the first power supply node 1910 receiving power supply voltage Vcc, and a second power supply line 1912 is arranged parallel to the first power supply line 1911. First power supply line 1911 is connected to second power supply line 1912 by means of a high resistance Ra. Parallel to the resistance Ra, a p channel MOS transistor Q1 for selectively connecting first power supply line 1911 and second power supply line 1912 in response to a control signal .phi.c is provided. Between the first and second power supply lines 1911 and 1912, a capacitor Ca having a relatively large capacitance for stabilizing the potential of second power supply line 1912 is provided.
A transmission path of the other power supply voltage Vss (ground potential:0 V) includes a third power supply line 1921 connected to a second power supply node 1920 receiving the other power supply voltage (hereinafter simply referred to as the ground voltage) Vss, and a fourth power supply line 1922 arranged parallel to the third power supply line 1921. Between the third and fourth power supply lines 1921 and 1922, a high resistance Rb is provided, and parallel to the resistance Rb, there is provided an n channel MOS transistor Q2 for selectively connecting the third power supply line 1921 and the fourth power supply line 1922 in response to a control signal .phi.s. Between the third and fourth power supply lines 1921 and 1922, a capacitor Cb having large capacitance for stabilizing the potential of the fourth power supply line 1922 is provided.
Inverters f1, f3, . . . of odd-numbered stages have one operating power supply node (power supply node receiving a high potential) connected to first power supply line 1911 and the other power supply node (power supply node receiving a low potential) connected to fourth power supply line 1922. Inverters f2, . . . of even-numbered stages have one operating power supply node connected to second power supply line 1912 and the other power supply node connected to third power supply line 1921. The operation will be described.
In a DRAM, a signal state at a stand-by state can be predicted in advance. The state of an output signal is also predictable. In the structure shown in FIG. 62, input signal IN attains to the low level at the stand-by state and attains to the high level in an active cycle. In a stand-by cycle, control signal .phi.c is set to the high level, control signal .phi.s is set to the low level and MOS transistors Q1 and Q2 are both turned off. At this state, power supply lines 1911 and 1912 are connected through high resistance Ra, while power supply lines 1921 and 1922 are connected through high resistance Rb. The potential VCL of power supply line 1912 is EQU VCL=Vcc-Ia.multidot.Ra
while the voltage VSL of power supply line 1922 is EQU VSL=Vss+Ib.multidot.Rb
where Ia and Ib represent currents flowing through resistances Ra and Rb, respectively. It is assumed that input signal IN is at the ground potential level Vss. In inverter f1, p channel MOS transistor PT is on, charging the output node to the power supply potential Vcc level on power supply line 1911. Meanwhile, source potential (potential of power supply node 1920) of n channel MOS transistor NT is the intermediate potential VSL, and set at a potential level higher than the ground potential Vss. Therefore, the gate-source voltage of n channel MOS transistor NT becomes negative, the subthreshold current corresponds to the subthreshold current IL2 when the gate-source voltage is -VSL, and is smaller than the subthreshold current IL1 flowing when the potential at power supply node 1902 is at the ground potential Vss, as shown in FIG. 61.
The operating characteristics of the MOS transistor will be described in accordance with the line I shown in FIG. 61. As for the on/off state of n channel MOS transistor, the state where the gate-source voltage is higher than the threshold voltage is referred to as the on state, and the state where the gate-source voltage is smaller than the threshold voltage is referred to as the off state. The relation is reversed in a p channel MOS transistor.
In inverter f2, the input signal/IN (output signal from inverter f1) is at the high level of the power supply potential Vcc. Therefore, in inverter f2, p channel MOS transistor is off and n channel MOS transistor is on. The p channel MOS transistor has its source connected to power supply line 1912 receiving the voltage VCL. Therefore, in inverter f2, the gate potential of p channel MOS transistor is higher than the source potential, and as in the n channel MOS transistor, the subthreshold current is also suppressed. This also applies to inverters f3 to fn of the succeeding stages. Therefore, in the stand-by state, subthreshold current in inverters f1 to fn is suppressed, and the stand-by current can be reduced.
When an active cycle starts, control signal .phi.c is set to the low level and control signal .phi.s is set to the high level. MOS transistors Q1 and Q2 are both turned on. MOS transistors Q1 and Q2 have large channel width W, and are capable of supplying sufficient charging/discharging current to inverters f1 to fn. At this state, potentials of power supply lines 1912 and 1922 are at the levels of the power supply potential Vcc and the ground potential Vss, respectively. Therefore, in the active cycle, the output signal OUT is set to the established state in accordance with the input signal IN.
FIG. 63 shows signal waveforms of the circuit shown in FIG. 62 and current flowing through the power supply lines. Referring to FIG. 63, in the stand-by cycle, MOS transistors Q1 and Q2 are both off in response to signals .phi.s and .phi.c, and the voltage VCL on power supply line 1912 and the voltage VSL of power supply line 1922 are at intermediate potentials between power supply voltage Vcc and ground potential Vcc (0 V), respectively. At this stage, MOS transistors in the subthreshold region (MOS transistors which are off) of inverters f1 to f4 are set more strongly off, thus reducing subthreshold current.
However, in the active cycle, control signals .phi.s and .phi.c are set to the high level and low level, respectively, MOS transistors Q1 and Q2 are turned on, the voltage VCL on power supply line 1912 becomes equal to the power supply potential Vcc and voltage VSL on power supply line 1922 becomes equal to the ground potential Vss. At the start of an active cycle, the power supply current Icc (VCL charging current) flows for charging power supply line 1912 and when input signal IN changes subsequently, inverters f1 to fn operate in response, charging/discharging current is generated for changing the respective signal levels, and thus a relatively large operating current flows.
In the active cycle, the voltage VCL is set to be equal to power supply potential Vcc, while the power supply voltage VSL is set equal to the ground potential Vss. Therefore, in inverters f1 to f4, the gate potential and the source potential of a transistor which is off are equal to each other. Therefore, when an MOS transistor having small absolute value Vth of the threshold voltage is used, considerably large subthreshold current flows. Namely, in the active cycle, before and after the change of the input signal IN, a large subthreshold current (active DC current) flows, causing a problem of a large current consumption in the active cycle. Especially in a semiconductor memory device having large storage capacity such as a 1 giga bit DRAM, when the number of MOS transistors which are the components of the device is increased, total sum of the active DC current is too large to be negligible.
In transistors Q1 and Q2 (see FIG. 62) which are turned off in the standby cycle, subthreshold current flows in the stand-by cycle. When the absolute values of the threshold voltages of transistors Q1 and Q2 are increased so as to reduce the subthreshold current flowing through transistors Q1 and Q2 in the stand-by cycle, the time necessary for recovering the potentials of power supply lines 1912 and 1922 at the transition into the active cycle becomes longer from the reason which will be described in the following, causing the problem that the access time of the semiconductor memory device becomes longer.
More specifically, at the transition from the stand-by cycle to the active cycle, it takes long period of time for the transistors Q1 and Q2 to operate in the saturated region as the absolute value of the threshold voltage of the transistors Q1 and Q2 is high. Thus, the transistors operate in the nonsaturated region for a long period of time. Therefore, as compared with an example in which the threshold value of the MOS transistor is small, current drivability of transistors Q1 and Q2 at the transition from the stand-by cycle to the active cycle becomes smaller, retarding recovery of potentials on power supply lines 1921 and 1922. It is necessary that internal circuitry is activated after the potentials on power supply lines 1921 and 1922 becomes stable. This means that the start of operation of the internal circuitry is delayed, and in the case of a semiconductor memory device, the access time becomes longer.